1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming single and double diffusion breaks on integrated circuit (IC) products comprised of FinFET devices and the resulting IC products.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 wherein the fins 14 of the device 10 are made of the material of the substrate 12, e.g., silicon. The device 10 includes a plurality of trenches 13, three illustrative fins 14, a gate structure 16, a sidewall spacer 18 and a gate cap layer 20. An isolation material 17 provides electrical isolation between the fins 14. In more advanced devices, the gate structure 16 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material, and one or more conductive material layers that serve as the gate electrode for the device 10. The fins 14 have a three dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device 10 when it is operational. The portions of the fins 14 covered by the gate structure 16 are the channel regions of the FinFET device 10. The portions of the fins 14 that are positioned outside of the spacers 18 will become part of the source/drain regions of the device 10.
When an appropriate voltage is applied to the gate electrode 16 of a FinFET device 10, the surfaces (and the inner portion near the surface) of the fins 14, i.e., the vertically oriented sidewalls and the top upper surface of the fin, form a surface inversion layer or a volume inversion layer that contributes to current conduction. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current than traditional planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production costs relative to previous device generations. Thus, device designers spend a great amount of time and effort to maximize device performance while seeking ways to reduce manufacturing costs and improve manufacturing reliability. As it relates to 3D devices, device designers have spent many years and employed a variety of techniques in an effort to improve the performance, capability and reliability of such devices. One technique involves forming FinFET devices with stressed channel regions to enhance device performance (a compressively stressed channel region for a PMOS device and a tensile stressed channel region for an NMOS device). Additionally, device designers are currently investigating using alternative semiconductor materials for the channel regions of such FinFET devices, such as SiGe, Ge and III-V materials, to enhance the performance capabilities of such devices, e.g., to enable low-voltage operation without degrading their operating speed.
FIG. 1B is a perspective view of an illustrative prior art FinFET semiconductor device 10, wherein the overall fin structure of the device includes a substrate fin portion 14A and an alternative fin material portion 14B. As with the case above, the substrate fin portion 14A may be made of silicon, i.e., the same material as the substrate 12, and the alternative fin material portion 14B may be made of a material other than the substrate material, for example, silicon-germanium, substantially pure germanium, III-V materials, etc. As noted above, the use of such alternative fin materials improves the mobility of charge carriers in the device.
One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique. In the replacement gate technique, a so-called “dummy” or sacrificial gate structure is initially formed and remains in place as many process operations are performed to form the device, e.g., the formation of doped source/drain regions, formation of epi semiconductor material in the source/drain regions of the device, performing an anneal process to repair damage to the substrate caused by the ion implantation processes and to activate the implanted dopant materials, etc. At some point in the process flow, the sacrificial gate structure is removed to define a gate cavity where the final HK/MG replacement gate structure for the device is formed.
The various transistor devices that are formed for an IC product must be electrically isolated from one another to properly function in an electrical circuit. Typically, this is accomplished by forming a trench in the substrate 12, and filling the trench with an insulating material, such as silicon dioxide. Within the industry, these isolation regions may sometimes be referred to as “diffusion breaks.” However, the formation of such isolation structures consumes very valuable plot space on the substrate 12. Moreover, in some applications, such as those integrated circuit products employing FinFET transistor devices, as device sizes have decreased, and packing densities have increased, it is sometimes difficult to form the desired isolation region made of an insulating material.
In one illustrative prior art process flow, the fins for an integrated circuit are initially formed uniformly across the entire substrate (i.e., a “sea of fins”). Thereafter, portions of the fins are removed to define regions where isolation regions will be formed to electrically isolate the various devices. Cutting the desired portions of the fins is typically accomplished by forming a so-called “fin cut” patterned etch mask with openings corresponding to the portions of the fins to be removed. The space previously occupied by the removed portions of the fins is then filled with an insulating material. After the fins are cut, and the isolation regions are formed, the gate structures are then formed across the fins. In the case where a replacement gate process is used to manufacture the FinFET devices, the initial gate structures are sacrificial gate structures that will subsequently be removed and replaced with final gate structures for the devices. As mentioned above, several process operations are performed after the formation of the sacrificial gate structures, e.g., the formation of epi semiconductor material in the source/drain regions of the device. When the epi semiconductor material is formed in the source/drain regions, it is important that the epi material not form in unwanted areas of the devices so as to not create a multitude of problems, e.g., growing around the end of a gate structure so as to create a short circuit between the source region and drain region, bridging the space between two adjacent active regions, etc. Thus, with reference to FIG. 1C, when the fins are cut, the cut is located such that the cut ends of the fins will be positioned under the dummy gate structures when they are formed. This is sometimes referred to as the fins being “tucked” in the sense that the cut end of the fin is positioned under or “tucked under” the dummy gate structure. Such a tucked fin arrangement is required on integrated circuits having arrangements similar to that depicted in FIG. 1C so as to prevent the undesirable formation of epi semiconductor material in the space between the two dummy gates and to produce uniform source/drain regions (when the epi material is formed) for all of the devices so as to avoid variances in device performance.
Unfortunately, performing the fin cut process prior to formation of the gate structures can be detrimental as it relates to retaining desired stress conditions (e.g., compressive or tensile) when the fins are cut as there is no “anchoring structure” such as gate structures to source/drain epi material to help maintain or at least reduce the loss of some of the desired stress profiles created in the fins. This is particularly true when using alternative semiconductor materials for the channel region of the FinFET devices.
FIGS. 1C and 1D depict a FinFET based integrated circuit product comprised of two FinFET devices that are each formed above a separate active region with isolation material (not shown) positioned between the two active regions. In this example, each of the devices comprises a single active gate. Dummy gates are formed to cover the edges of the active regions so that the fins may be tucked for the reasons described above. FIG. 1C is a configuration that is referred to as a double diffusion break (DDB) wherein the lateral width 30 (in the current transport direction or gate length direction of the FinFET devices) of the isolation material between the two active regions approximately corresponds to the lateral width of two of the gate structures. FIG. 1D is a configuration that is referred to as a single diffusion break (SDB) wherein the lateral width 32 (in the current transport direction or gate length direction of the FinFET devices) of the isolation material between the two active regions is less than the lateral width of a single gate structure. In general, it is easier to form a double diffusion break (DDB) isolation structure than it is to form a single diffusion break (SDB) due to the relatively larger size of the double diffusion break (DDB) isolation structure. However, the use of such double diffusion break (DDB) isolation structures consumes more of the available plot space on a substrate than does the use of single diffusion break (SDB) isolation structures, thereby leading to reduced packing densities. Some integrated circuit products use both double diffusion break (DDB) and single diffusion break (SDB) isolation structures in different regions of a product. For example, logic regions of an integrated circuit product may employ single diffusion break (SDB) isolation structures, whereas SRAM regions may employ double diffusion break (DDB) isolation structures.
As noted above, one problem that can arise is loss of or reduction in desired stress profiles (compressive or tensile) that are intentionally created in fins when the fins are cut prior to forming any supporting structure, e.g., gates and/or source/drain epi material. One possible option would be to perform the fin cut process after the formation of gate structures (such as sacrificial gate structures) around the fins. FIGS. 1E and 1F depict an example wherein an opening 34 in a fin cut mask is shown (FIG. 1E) that exposes the fins to be removed. While cutting the fins after formation of the gate structures can be readily performed when forming double diffusion break (DDB) isolation structures, such a process will not work when forming single diffusion break (SDB) isolation structures because the portions of the fins to be removed are covered by a gate structure.
Another possibility would be to perform the fin cut process after sacrificial gate structures are removed when forming FinFET devices using replacement gate manufacturing techniques. That is, the fins to be removed would be cut by performing an etching process through the replacement gate cavity that is created after the sacrificial gate structure is removed. FIGS. 1G and 1H depict an example wherein an opening 36 in a fin cut mask is shown (FIG. 1H) that would be aligned with such a replacement gate cavity. As an initial matter, it would be very challenging to properly align the opening 36 with the replacement gate cavity. Nevertheless, such an approach may be possible when forming single diffusion break (SDB) structures. However, such an approach is more problematic when forming double diffusion break (DDB) isolation structures. More specifically, at the point in a typical replacement gate process when the sacrificial gate structure is removed, the fins are covered by an insulating material, e.g., silicon dioxide. Thus, while removal of the portions of the fins exposed within the two laterally adjacent replacement gate cavities might be possible, such a process would leave portions of the fins positioned between the two active regions, i.e., the portions of the fins between the two laterally adjacent replacement gate cavities. The presence of such residual fin material may lead to an undesirable increase in capacitance. In cases where both double diffusion break (DDB) isolation structures and single diffusion break (SDB) isolation structures are formed, it would be possible to form both of such structures after formation of the gate structures, but it would involve formation of two separate cut masks—one mask for the DDB structures and another mask for the SDB structures—which would add to processing costs and complexity.
The present disclosure is directed to methods of forming single and double diffusion breaks on IC products comprised of FinFET devices and the resulting products that may solve or reduce one or more of the problems identified above.